RISC-V cacheline zero

The cbo.zero instruction was added to RISC-V in early 2022 as part of the "Zicboz" extension (https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.pdf). I assume it's going to be available on any forthcoming RISC-V HPC processor (e.g. the Ventana Veyron V1). It is supported by Clang 15+ and GCC 11+.

However, we still need to wait for the QEMU 8 release (https://github.com/qemu/qemu/commit/a939c500793ae7672defe5e3dc83220576a7b202) before we can test it in CI. The multiarch Docker images (https://github.com/multiarch/qemu-user-static) sometimes take a few months after the corresponding QEMU release. If they go straight to QEMU 8.1, we can also switch on SIMD autodetection (https://github.com/qemu/qemu/commit/4333f0924c2f2ca8efaebaed8c24f55f77d8b013).

Requires https://i10git.cs.fau.de/pycodegen/pycodegen/-/merge_requests/16

src/pystencils/backends/riscv_instruction_sets.py

@@ -98,9 +98,12 @@ def get_vector_instruction_set_riscv(data_type='double', instruction_set='rvv'):
     result['int'] = f'vint{bits["int"]}m1_t'
     result['bool'] = f'vbool{bits[data_type]}_t'
 
-    result['headers'] = ['<riscv_vector.h>']
+    result['headers'] = ['<riscv_vector.h>', '"riscv_v_helpers.h"']
 
     result['any'] += ' > 0x0'
     result['all'] += f' == vsetvl_e{bits[data_type]}m1({vl})'
 
+    result['cachelineSize'] = 'cachelineSize()'
+    result['cachelineZero'] = 'cachelineZero((void*) {0})'
+
     return result