Compatibility with latest RISCV64 and ARM CI image

Follow-up to 1022af98 after upgrading to the latest compilers. ARM SVE also appears stable on latest Clang without weird workarounds now.

Depends on https://i10git.cs.fau.de/pycodegen/pycodegen/-/merge_requests/15

pystencils/backends/riscv_instruction_sets.py

@@ -50,8 +50,8 @@ def get_vector_instruction_set_riscv(data_type='double', instruction_set='rvv'):
         '|': 'mor_mm[0, 1]',
 
         'blendv': 'merge_vvm[2, 0, 1]',
-        'any': 'popc_m[0]',
-        'all': 'popc_m[0]',
+        'any': 'cpop_m[0]',
+        'all': 'cpop_m[0]',
     }
 
     result = dict()