Compatibility with latest RISCV64 and ARM CI image

Follow-up to 1022af98 after upgrading to the latest compilers. ARM SVE also appears stable on latest Clang without weird workarounds now.

Depends on https://i10git.cs.fau.de/pycodegen/pycodegen/-/merge_requests/15

.gitlab-ci.yml

@@ -171,24 +171,18 @@ ppc64le:
     - sed -i s/mcpu=native/mcpu=power8/g ~/.config/pystencils/config.json
 
 arm64v9:
-  # Compiler support for SVE is still pretty rough: GCC 10+11 produce incorrect code for fixed-width vectors,
-  # while Clang 12 produces memory-corrupting heisenbugs unless we enable the address sanitizer.
-  # In the RNG tests, GCC 10+11 produce an internal compiler error.
-  # The memory corruption seems to only happen with qemu-user, not with qemu-system.
-  # Once the compilers and QEMU have improved, this job should be cleaned up to match the others.
+  # SVE support is still unreliable in GCC 11 (incorrect code for fixed-width vectors, internal compiler errors).
   extends: .multiarch_template
   image: i10git.cs.fau.de:5005/pycodegen/pycodegen/arm64:testing
   variables:
     PYSTENCILS_SIMD: "sve256,sve512,sve"
-    ASAN_OPTIONS: detect_leaks=0
-    LD_PRELOAD: /usr/lib/aarch64-linux-gnu/libasan.so.6
   before_script:
     - *multiarch_before_script
     - sed -i s/march=native/march=armv8-a+sve/g ~/.config/pystencils/config.json
     - sed -i s/g\+\+/clang++/g ~/.config/pystencils/config.json
 
 riscv64:
-  # The RISC-V vector extension are so new they are not supported by GCC yet.
+  # RISC-V vector extension are currently not supported by GCC.
   # Also, the image is built without the libomp package which is not yet available on Ubuntu.
   extends: .multiarch_template
   image: i10git.cs.fau.de:5005/pycodegen/pycodegen/riscv64:testing