Compatibility with latest RISCV64 and ARM CI image

Follow-up to 1022af98 after upgrading to the latest compilers. ARM SVE also appears stable on latest Clang without weird workarounds now.

Depends on https://i10git.cs.fau.de/pycodegen/pycodegen/-/merge_requests/15

.gitlab-ci.yml

@@ -154,7 +154,7 @@ ubuntu:
 
 arm64v8:
   extends: .multiarch_template
-  image: i10git.cs.fau.de:5005/pycodegen/pycodegen/arm64
+  image: i10git.cs.fau.de:5005/pycodegen/pycodegen/arm64:testing
   variables:
     PYSTENCILS_SIMD: "neon"
   before_script:
@@ -163,7 +163,7 @@ arm64v8:
 
 ppc64le:
   extends: .multiarch_template
-  image: i10git.cs.fau.de:5005/pycodegen/pycodegen/ppc64le
+  image: i10git.cs.fau.de:5005/pycodegen/pycodegen/ppc64le:testing
   variables:
     PYSTENCILS_SIMD: "vsx"
   before_script:
@@ -177,7 +177,7 @@ arm64v9:
   # The memory corruption seems to only happen with qemu-user, not with qemu-system.
   # Once the compilers and QEMU have improved, this job should be cleaned up to match the others.
   extends: .multiarch_template
-  image: i10git.cs.fau.de:5005/pycodegen/pycodegen/arm64
+  image: i10git.cs.fau.de:5005/pycodegen/pycodegen/arm64:testing
   variables:
     PYSTENCILS_SIMD: "sve256,sve512,sve"
     ASAN_OPTIONS: detect_leaks=0
@@ -191,7 +191,7 @@ riscv64:
   # The RISC-V vector extension is still experimental and needs special compiler flags.
   # Once they are officially released, this job should be cleaned up to match the others.
   extends: .multiarch_template
-  image: i10git.cs.fau.de:5005/pycodegen/pycodegen/riscv64
+  image: i10git.cs.fau.de:5005/pycodegen/pycodegen/riscv64:testing
   variables:
     PYSTENCILS_SIMD: "rvv"
     QEMU_CPU: "rv64,v=true"