Sizeless vectorization

Surprisingly easy follow-up to !232 (merged) to support sizeless ARM SVE and RISC-V V. It uses some ugly hacks to sneak C functions like svcntb() into places that expect Python integers. Python duck-typing and SymPy made it possible. Not sure whether this should be merged as-is, but making it nicer would require re-writing CBackend. At least I couldn't think of a better way to obtain the innermost loop counter and loop stop.

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• b30645cc - Sizeless SVE vectorization

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• 5880d6d3 - Sizeless SVE vectorization

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mentioned in merge request walberla/walberla!448 (merged)

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• 4d5650d5 - move NontemporalFence and CachelineSize to backend

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• c1a619e0 - don't hide C function inside TypedSymbol
• 66ab1f09 - vec_any/vec_all test for sizeless SVE

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• db4f654a - Merge branch 'master' into sve

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• 50b2a2c6 - Merge branch 'master' of i10git.cs.fau.de:pycodegen/pystencils into sve

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• 7e2aff1b - fix

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• 905bad2b - don't zero cachelines beyond the end of a field
• aeb02000 - Merge remote-tracking branch 'origin/master' into sve
• bf467c1f - Add ARM SVE CI job

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• 65e8127e - Add ARM SVE CI job

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• d80e7a2e - Add ARM SVE CI job

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• 8f667224 - Simplify the loop stop for sizeless SVE

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mentioned in merge request !245 (merged)

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• 17145997 - Sizeless SVE: don't change loop range

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mentioned in commit cc645538

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• 17145997...cc645538 - 7 commits from branch master
• 622e4f92 - Merge remote-tracking branch 'origin/master' into sve

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