WIP: ARM cache line zeroing

ARM has a cache line zero instruction that prevents data that will be overwritten anyway from being loaded from RAM. Kind of a light version of a non-temporal store. Saw this near the end of https://www.youtube.com/watch?v=BP7XD7JHgrI in the context of SVE, but might be relevant on Neon too. Just wanted to keep a note of this here.

Integrating this into pystencils is probably not completely straight-forward as you first need to check how much would be zeroed (64 bytes on all current chips, not guaranteed to match the cache line size), zero it, and then write the corresponding amount of data. Not sure if there are guarantees as to whether it's a multiple of the vector width.

There is not a whole lot of information for ARM, but the exact same thing has existed on IBM‘s PowerPC architecture (!228 (merged)) for decades. There, a cache line has 128 bytes (can be queried from the kernel via sysconf(_SC_LEVEL1_DCACHE_LINESIZE)) and can be zeroed with the __dcbz intrinsic.

pystencils/include/arm_neon_helpers.h

@@ -17,3 +17,32 @@ inline int32x4_t makeVec_s32(int a, int b, int c, int d)
     alignas(16) int data[4] = {a, b, c, d};
     return vld1q_s32(data);
 }
+
+// ZVA size is usually 64 bytes, but needs to be checked
+int zva_size() {
+    uint64_t dczid;
+    asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
+    if ((dczid & (1 << 4)) == 0) {
+        int size = 4 << (dczid & 0xf);
+        return size;
+    }
+    return 0;
+}
+
+// write zva_size bytes of float vectors to memory aligned to zva_size bytes
+inline void stream_f32(float32x4_t f[4], float* p) {
+    asm volatile("dc zva, %0"::"r"(p));
+    vst1q_f32(p, f[0]);
+    vst1q_f32(p, f[1]);
+    vst1q_f32(p, f[2]);
+    vst1q_f32(p, f[3]);
+}
+
+// write zva_size bytes of double vectors to memory aligned to zva_size bytes
+inline void stream_f64(float64x2_t f[4], double* p) {
+    asm volatile("dc zva, %0"::"r"(p));
+    vst1q_f64(p, f[0]);
+    vst1q_f64(p, f[1]);
+    vst1q_f64(p, f[2]);
+    vst1q_f64(p, f[3]);
+}