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pycodegen
pystencils
Commits
b1c5e21f
Commit
b1c5e21f
authored
2 years ago
by
Michael Kuron
Committed by
Michael Kuron
2 years ago
Browse files
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Plain Diff
Remove support for non-power-of-2 SVE vector widths
parent
967a5579
No related branches found
No related tags found
1 merge request
!325
Remove support for non-power-of-2 SVE vector widths
Pipeline
#52037
passed
2 years ago
Stage: pretest
Stage: test
Changes
3
Pipelines
1
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3 changed files
.gitlab-ci.yml
+1
-1
1 addition, 1 deletion
.gitlab-ci.yml
pystencils/backends/arm_instruction_sets.py
+2
-4
2 additions, 4 deletions
pystencils/backends/arm_instruction_sets.py
pystencils/backends/simd_instruction_sets.py
+5
-9
5 additions, 9 deletions
pystencils/backends/simd_instruction_sets.py
with
8 additions
and
14 deletions
.gitlab-ci.yml
+
1
−
1
View file @
b1c5e21f
...
@@ -175,7 +175,7 @@ arm64v9:
...
@@ -175,7 +175,7 @@ arm64v9:
extends
:
.multiarch_template
extends
:
.multiarch_template
image
:
i10git.cs.fau.de:5005/pycodegen/pycodegen/arm64
image
:
i10git.cs.fau.de:5005/pycodegen/pycodegen/arm64
variables
:
variables
:
PYSTENCILS_SIMD
:
"
sve256,sve512,sve"
PYSTENCILS_SIMD
:
"
sve128,
sve256,sve512,sve"
before_script
:
before_script
:
-
*multiarch_before_script
-
*multiarch_before_script
-
sed -i s/march=native/march=armv8-a+sve/g ~/.config/pystencils/config.json
-
sed -i s/march=native/march=armv8-a+sve/g ~/.config/pystencils/config.json
...
...
This diff is collapsed.
Click to expand it.
pystencils/backends/arm_instruction_sets.py
+
2
−
4
View file @
b1c5e21f
...
@@ -151,9 +151,7 @@ def get_vector_instruction_set_arm(data_type='double', instruction_set='neon'):
...
@@ -151,9 +151,7 @@ def get_vector_instruction_set_arm(data_type='double', instruction_set='neon'):
result
[
'
any
'
]
=
f
'
vaddlvq_u8(vreinterpretq_u8_u
{
bits
[
data_type
]
}
({{0}})) > 0
'
result
[
'
any
'
]
=
f
'
vaddlvq_u8(vreinterpretq_u8_u
{
bits
[
data_type
]
}
({{0}})) > 0
'
result
[
'
all
'
]
=
f
'
vaddlvq_u8(vreinterpretq_u8_u
{
bits
[
data_type
]
}
({{0}})) == 16*0xff
'
result
[
'
all
'
]
=
f
'
vaddlvq_u8(vreinterpretq_u8_u
{
bits
[
data_type
]
}
({{0}})) == 16*0xff
'
if
instruction_set
==
'
sve
'
or
bitwidth
&
(
bitwidth
-
1
)
==
0
:
result
[
'
cachelineSize
'
]
=
'
cachelineSize()
'
# only power-of-2 vector sizes will evenly divide a cacheline
result
[
'
cachelineZero
'
]
=
'
cachelineZero((void*) {0})
'
result
[
'
cachelineSize
'
]
=
'
cachelineSize()
'
result
[
'
cachelineZero
'
]
=
'
cachelineZero((void*) {0})
'
return
result
return
result
This diff is collapsed.
Click to expand it.
pystencils/backends/simd_instruction_sets.py
+
5
−
9
View file @
b1c5e21f
import
math
import
os
import
os
import
platform
import
platform
from
ctypes
import
CDLL
from
ctypes
import
CDLL
...
@@ -86,15 +85,12 @@ def get_supported_instruction_sets():
...
@@ -86,15 +85,12 @@ def get_supported_instruction_sets():
if
flags
.
issuperset
(
required_sve_flags
):
if
flags
.
issuperset
(
required_sve_flags
):
if
platform
.
system
()
==
'
Linux
'
:
if
platform
.
system
()
==
'
Linux
'
:
libc
=
CDLL
(
'
libc.so.6
'
)
libc
=
CDLL
(
'
libc.so.6
'
)
native_
length
=
8
*
libc
.
prctl
(
51
,
0
,
0
,
0
,
0
)
# PR_SVE_GET_VL
length
=
8
*
libc
.
prctl
(
51
,
0
,
0
,
0
,
0
)
# PR_SVE_GET_VL
if
native_
length
<
0
:
if
length
<
0
:
raise
OSError
(
"
SVE length query failed
"
)
raise
OSError
(
"
SVE length query failed
"
)
pwr2_length
=
int
(
2
**
math
.
floor
(
math
.
log2
(
native_length
)))
while
length
>
128
:
if
pwr2_length
%
256
==
0
:
result
.
append
(
f
"
sve
{
length
}
"
)
result
.
append
(
f
"
sve
{
pwr2_length
//
2
}
"
)
length
//=
2
if
native_length
!=
pwr2_length
:
result
.
append
(
f
"
sve
{
pwr2_length
}
"
)
result
.
append
(
f
"
sve
{
native_length
}
"
)
result
.
append
(
"
sve
"
)
result
.
append
(
"
sve
"
)
return
result
return
result
...
...
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