Example_SandyBridgeEP_E5-2680.yml

kerncraft version: 0.8.6.dev0
model name: Intel(R) Xeon(R) CPU E5-2680 0 @ 2.70GHz
model type: Intel Xeon SandyBridge EN/EP processor
clock: 2.7 GHz

sockets: 2
cores per socket: 8
threads per core: 2
NUMA domains per socket: 1
cores per NUMA domain: 8
transparent hugepage: always

in-core model: !!omap
  - IACA: SNB
  - OSACA: SNB
  - LLVM-MCA: -mcpu=sandybridge
isa: x86

FLOPs per cycle:
  SP: {total: 16, ADD: 8, MUL: 8}
  DP: {total: 8, ADD: 4, MUL: 4}

compiler: !!omap
- icc: -O3 -xAVX -fno-alias -qopenmp -ffreestanding -nolib-inline
- clang: -O3 -march=corei7-avx -mtune=corei7-avx -D_POSIX_C_SOURCE=200809L -fopenmp -ffreestanding
- gcc: -O3 -march=corei7-avx -D_POSIX_C_SOURCE=200809L -fopenmp -lm -ffreestanding

overlapping model:
  ports: 
    IACA: ['0', 0DV, '1', '2', '3', '4', '5']
    OSACA: ['0', 0DV, '1', '2', '3', '4', '5']
    LLVM-MCA: [SBDivider, SBFPDivider, SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]
  performance counter metric: Max(UOPS_DISPATCHED_PORT_PORT_0:PMC[0-3], UOPS_DISPATCHED_PORT_PORT_1:PMC[0-3], UOPS_DISPATCHED_PORT_PORT_4:PMC[0-3], UOPS_DISPATCHED_PORT_PORT_5:PMC[0-3])
non-overlapping model:
  ports: 
    IACA: [2D, 3D]
    OSACA: [2D, 3D]
    LLVM-MCA: [SBPort23]
  performance counter metric: T_nOL + T_L1L2 + T_L2L3 + T_L3MEM

cacheline size: 64 B
memory hierarchy:
- level: L1
  cache per group: {sets: 64, ways: 8, cl_size: 64, replacement_policy: LRU, write_allocate: true,
    write_back: true, load_from: L2, store_to: L2}
  cores per group: 1
  threads per group: 2
  groups: 16
  performance counter metrics:
    accesses: MEM_UOPS_RETIRED_LOADS:PMC[0-3] + MEM_UOPS_RETIRED_STORES:PMC[0-3]
    misses: L1D_REPLACEMENT:PMC[0-3]
    evicts: L1D_M_EVICT:PMC[0-3]
  upstream throughput: [architecture code analyzer, [2D, 3D]]
  transfers overlap: false
- level: L2
  cache per group: {sets: 512, ways: 8, cl_size: 64, replacement_policy: LRU, write_allocate: true,
    write_back: true, load_from: L3, store_to: L3}
  cores per group: 1
  threads per group: 2
  groups: 16
  upstream throughput: [32 B/cy, half-duplex]
  transfers overlap: false
  performance counter metrics:
    accesses: L1D_REPLACEMENT:PMC[0-3] + L1D_M_EVICT:PMC[0-3]
    misses: L2_LINES_IN_ALL:PMC[0-3]
    evicts: L2_TRANS_L2_WB:PMC[0-3]
- level: L3
  cache per group: {sets: 20480, ways: 16, cl_size: 64, replacement_policy: LRU, write_allocate: true,
    write_back: true}
  cores per group: 8