From 78d7192df670791925f017b2a7413ff3ae7478d2 Mon Sep 17 00:00:00 2001
From: Rafael Ravedutti <rafaelravedutti@gmail.com>
Date: Sat, 27 Nov 2021 01:22:19 +0100
Subject: [PATCH] Add first compilable version separated in modules
Signed-off-by: Rafael Ravedutti <rafaelravedutti@gmail.com>
---
src/pairs/code_gen/cgen.py | 2 +-
src/pairs/sim/pbc.py | 10 +++++-----
src/pairs/sim/simulation.py | 10 +++++++++-
3 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/src/pairs/code_gen/cgen.py b/src/pairs/code_gen/cgen.py
index d6261dc..51ada58 100644
--- a/src/pairs/code_gen/cgen.py
+++ b/src/pairs/code_gen/cgen.py
@@ -326,7 +326,7 @@ class CGen:
if isinstance(ast_node, Deref):
var = self.generate_expression(ast_node.var)
- return f"*{var}"
+ return f"(*{var})"
if isinstance(ast_node, Iter):
assert mem is False, "Iterator is not lvalue!"
diff --git a/src/pairs/sim/pbc.py b/src/pairs/sim/pbc.py
index 08a5d96..f91dd13 100644
--- a/src/pairs/sim/pbc.py
+++ b/src/pairs/sim/pbc.py
@@ -89,12 +89,12 @@ class SetupPBC(Lowerable):
sim.check_resize(pbc_capacity, npbc)
npbc.set(0)
- for i in For(sim, 0, nlocal + npbc):
- pos = positions[i]
- last_id = nlocal + npbc
- last_pos = positions[last_id]
+ for d in range(0, ndims):
+ for i in For(sim, 0, nlocal + npbc):
+ pos = positions[i]
+ last_id = nlocal + npbc
+ last_pos = positions[last_id]
- for d in range(0, ndims):
grid_length = grid.length(d)
# TODO: VecFilter?
for _ in Filter(sim, pos[d] < grid.min(d) + cutneigh):
diff --git a/src/pairs/sim/simulation.py b/src/pairs/sim/simulation.py
index 8e30895..8ef7b4f 100644
--- a/src/pairs/sim/simulation.py
+++ b/src/pairs/sim/simulation.py
@@ -71,7 +71,15 @@ class Simulation:
self.module_list.append(module)
def modules(self):
- return self.module_list
+ sorted_mods = []
+ main_mod = None
+ for m in self.module_list:
+ if m.name != 'main':
+ sorted_mods.append(m)
+ else:
+ main_mod = m
+
+ return sorted_mods + [main_mod]
def ndims(self):
return self.dims
--
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