From 595e757740009c7a715e38865e12393287122234 Mon Sep 17 00:00:00 2001
From: Rafael Ravedutti <rafaelravedutti@gmail.com>
Date: Tue, 15 Feb 2022 00:38:47 +0100
Subject: [PATCH] Add debug option and fix resize logic
Signed-off-by: Rafael Ravedutti <rafaelravedutti@gmail.com>
---
examples/lj_func.py | 2 +-
src/pairs/__init__.py | 4 ++--
src/pairs/code_gen/cgen.py | 11 ++++++++++-
src/pairs/transformations/modules.py | 9 +++++----
4 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/examples/lj_func.py b/examples/lj_func.py
index 5ec2c46..97d7200 100644
--- a/examples/lj_func.py
+++ b/examples/lj_func.py
@@ -19,7 +19,7 @@ sigma = 1.0
epsilon = 1.0
sigma6 = sigma ** 6
-psim = pairs.simulation("lj_ns")
+psim = pairs.simulation("lj_ns", debug=True)
psim.add_real_property('mass', 1.0)
psim.add_position('position')
psim.add_vector_property('velocity')
diff --git a/src/pairs/__init__.py b/src/pairs/__init__.py
index 5bb8d84..98e050f 100644
--- a/src/pairs/__init__.py
+++ b/src/pairs/__init__.py
@@ -2,5 +2,5 @@ from pairs.code_gen.cgen import CGen
from pairs.sim.simulation import Simulation
-def simulation(ref, dims=3, timesteps=100):
- return Simulation(CGen(f"{ref}.cpp"), dims, timesteps)
+def simulation(ref, dims=3, timesteps=100, debug=False):
+ return Simulation(CGen(f"{ref}.cpp", debug), dims, timesteps)
diff --git a/src/pairs/code_gen/cgen.py b/src/pairs/code_gen/cgen.py
index 51ada58..af7b1a6 100644
--- a/src/pairs/code_gen/cgen.py
+++ b/src/pairs/code_gen/cgen.py
@@ -32,8 +32,9 @@ class CGen:
else 'bool'
)
- def __init__(self, output):
+ def __init__(self, output, debug=False):
self.sim = None
+ self.debug = debug
self.print = Printer(output)
def assign_simulation(self, sim):
@@ -88,7 +89,15 @@ class CGen:
self.print(f"void {module.name}({module_params}) {{")
self.print.add_indent(4)
+
+ if self.debug:
+ self.generate_statement(Print(self.sim, module.name + " --- enter"))
+
self.generate_statement(module.block)
+
+ if self.debug:
+ self.generate_statement(Print(self.sim, module.name + " --- exit"))
+
self.print.add_indent(-4)
self.print("}")
diff --git a/src/pairs/transformations/modules.py b/src/pairs/transformations/modules.py
index c463bea..695bce0 100644
--- a/src/pairs/transformations/modules.py
+++ b/src/pairs/transformations/modules.py
@@ -115,9 +115,9 @@ class AddResizeLogic(Mutator):
resizes = list(self.module_resizes[module].keys())
capacities = list(self.module_resizes[module].values())
resize_id = resizes[capacities.index(match_capacity)]
- return Branch(ast_node.sim, src < match_capacity,
- blk_if=Block(ast_node.sim, ast_node),
- blk_else=Block(ast_node.sim, ast_node.sim.resizes[resize_id].set(src)))
+ return Branch(ast_node.sim, src + 1 >= match_capacity,
+ blk_if=Block(ast_node.sim, ast_node.sim.resizes[resize_id].set(src)),
+ blk_else=Block(ast_node.sim, ast_node))
return ast_node
@@ -181,7 +181,8 @@ class ReplaceModulesByCalls(Mutator):
if properties.is_capacity(c):
for p in properties.all():
- sizes = [c, sim.ndims()] if p.type() == Type_Vector else [c]
+ new_capacity = sum(properties.capacities)
+ sizes = [new_capacity, sim.ndims()] if p.type() == Type_Vector else [new_capacity]
props_realloc += [Realloc(sim, p, reduce(operator.mul, sizes)), UpdateProperty(sim, p, sizes)]
resize_stmts.append(
--
GitLab