From 50d1e3f00b5fc8403e1a8dc4a8c8cc2e7f549aa0 Mon Sep 17 00:00:00 2001
From: Behzad Safaei <iwia103h@alex2.nhr.fau.de>
Date: Tue, 28 Jan 2025 13:08:31 +0100
Subject: [PATCH] Remove do_timestep
---
src/pairs/code_gen/cgen.py | 16 +++-------------
src/pairs/sim/simulation.py | 2 --
2 files changed, 3 insertions(+), 15 deletions(-)
diff --git a/src/pairs/code_gen/cgen.py b/src/pairs/code_gen/cgen.py
index 27093c5..7649f4f 100644
--- a/src/pairs/code_gen/cgen.py
+++ b/src/pairs/code_gen/cgen.py
@@ -380,7 +380,7 @@ class CGen:
self.print.end()
- def generate_library(self, update_cells_module, user_defined_modules, initialize_module, create_domain_module, setup_sim_module, do_timestep_module, reverse_comm_module, communicate_module, reset_volatiles_module):
+ def generate_library(self, update_cells_module, user_defined_modules, initialize_module, create_domain_module, setup_sim_module, reverse_comm_module, communicate_module, reset_volatiles_module):
self.generate_interfaces()
# Generate CUDA/CPP file with modules
ext = ".cu" if self.target.is_gpu() else ".cpp"
@@ -414,7 +414,7 @@ class CGen:
self.generate_kernel(kernel)
for module in self.sim.modules():
- if module.name not in ['update_cells', 'initialize', 'create_domain', 'setup_sim', 'do_timestep', 'reverse_comm', 'communicate', 'reset_volatiles']:
+ if module.name not in ['update_cells', 'initialize', 'create_domain', 'setup_sim', 'reverse_comm', 'communicate', 'reset_volatiles']:
if not module.user_defined:
self.generate_module(module)
@@ -440,7 +440,7 @@ class CGen:
self.generate_full_object_names = True
self.print("class PairsSimulation {")
- self.print("public:")
+ self.print("private:")
self.print(" PairsRuntime *pairs_runtime;")
self.print(" struct PairsObjects *pobj;")
self.print(" friend class PairsAccessor;")
@@ -495,16 +495,6 @@ class CGen:
self.print("}")
self.print("")
- # self.print("void do_timestep(int timestep) {")
- # self.print(" pobj->sim_timestep = timestep;")
- # self.print.add_indent(4)
- # self.generate_statement(do_timestep_module.block)
- # self.print.add_indent(-4)
- # self.print("}")
- # self.print("")
-
-
-
self.print("void reverse_comm() {")
self.generate_statement(reverse_comm_module.block)
self.print("}")
diff --git a/src/pairs/sim/simulation.py b/src/pairs/sim/simulation.py
index 5c665e4..20b4399 100644
--- a/src/pairs/sim/simulation.py
+++ b/src/pairs/sim/simulation.py
@@ -568,7 +568,6 @@ class Simulation:
])
setup_sim_module = Module(self, name='setup_sim', block=setup_sim)
- do_timestep_module = Module(self, name='do_timestep', block=timestep.as_block())
communicate_module = Module(self, name='communicate', block=Timestep(self, 0, comm_routine).as_block())
reset_volatiles_module = Module(self, name='reset_volatiles', block=Block(self, ResetVolatileProperties(self)))
@@ -597,7 +596,6 @@ class Simulation:
initialize_module,
create_domain_module,
setup_sim_module,
- do_timestep_module,
reverse_comm_module,
communicate_module,
reset_volatiles_module)
--
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