From 95564cf6ad5815cc5e7a6c310c23c5a9460170e8 Mon Sep 17 00:00:00 2001
From: Markus Holzer <markus.holzer@fau.de>
Date: Mon, 18 Sep 2023 11:20:09 +0200
Subject: [PATCH] Added better doc
---
pystencils/cpu/vectorization.py | 3 +++
1 file changed, 3 insertions(+)
diff --git a/pystencils/cpu/vectorization.py b/pystencils/cpu/vectorization.py
index 7c377944e..f39c52d81 100644
--- a/pystencils/cpu/vectorization.py
+++ b/pystencils/cpu/vectorization.py
@@ -185,6 +185,9 @@ def vectorize_inner_loops_and_adapt_load_stores(ast_node, assume_aligned, nontem
# the access is aligned or not. None of the current sizeless vector ISAs (SVE and RISC-V-V)
# have separate load/store instructions for aligned and unaligned, so there is no disadvantage
# to falling back to unaligned here. When new ISAs become available, this may need to be revisited.
+
+ # On sized vector ISAs that do not have separate instructions for aligned and unaligned access,
+ # alignment does not matter here either
aligned_access = False
else:
aligned_access = (index - loop_counter_symbol).subs(zero_loop_counters) % vector_width == 0
--
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