diff --git a/pystencils/cpu/vectorization.py b/pystencils/cpu/vectorization.py index 7c377944ea3db2e1200cb515fe27d63b8cdd953c..f39c52d81475f1deba8eeefa98e256f954755b54 100644 --- a/pystencils/cpu/vectorization.py +++ b/pystencils/cpu/vectorization.py @@ -185,6 +185,9 @@ def vectorize_inner_loops_and_adapt_load_stores(ast_node, assume_aligned, nontem # the access is aligned or not. None of the current sizeless vector ISAs (SVE and RISC-V-V) # have separate load/store instructions for aligned and unaligned, so there is no disadvantage # to falling back to unaligned here. When new ISAs become available, this may need to be revisited. + + # On sized vector ISAs that do not have separate instructions for aligned and unaligned access, + # alignment does not matter here either aligned_access = False else: aligned_access = (index - loop_counter_symbol).subs(zero_loop_counters) % vector_width == 0